Write VHDL or Verilog. Watch it light up.

A virtual FPGA board on your screen. Flip switches, press buttons and see your design come alive. No hardware needed.

Try online No installation needed
Download for Windows Windows installer
Download for Linux Linux · AppImage · x86-64

No hardware needed

Everything happens on screen, so you can practise anywhere.

Real VHDL and Verilog

The same code you would put on a real FPGA, run by GHDL (VHDL-2008) and Icarus Verilog. The Windows app ships GHDL 5.0.1 and Icarus 13.0.

Free for everyone

Open source, and free to use at home or in class.

Close-up of the virtual board: three red LEDs lit by the matching switches

Flip a switch. Your design reacts.

Switches, pushbuttons, LEDs and 7-segment displays respond to your design while it runs. It feels like the real board, without one on your desk.

This is real simulation, not a JavaScript imitation: your design runs in GHDL or Icarus Verilog, and every flip of a switch goes to it while it runs.

Flip the switches yourself in the live demo
Time to compile the same VHDL file
HDLBoard < 1 s
Quartus Prime Lite > 5 s

Measured with the same file on a Windows 11 laptop (Intel Core i7-1185G7, 32 GB): GHDL 5.0.1 checks it in 0.02 s, Quartus Prime Lite 25.1 needs 8.8 s for Analysis & Synthesis alone. A full Quartus compile takes longer.

HDLBoard

HDLBoard after compiling a VHDL file with two typos: lines 17 and 20 are tinted red with a cross in the margin, the wrong character is underlined, and each line ends with its error message, interfaces must be separated by ';' (found ','), and extra ';' at end of interface list
  • The lines with errors turn red in the editor
  • The exact spot is underlined
  • The message sits at the end of the line
  • Both typos are found in one compile

Quartus Prime Lite

Quartus Prime Lite after compiling the same code: the editor shows no marks, and the message list below shows error 10500, VHDL syntax error at MyTest.vhd(17) near text ','; expecting ';', or ')', and Analysis and Synthesis unsuccessful with 1 error
  • Nothing is marked in the editor
  • Error 10500 appears in a separate message list
  • Only the first typo is reported, so the second costs another compile

Test your design. Side by side.

Automatically places your test and design. Press play to see the results.

HDLBoard in split view: the AND gate truth-table testbench on the left, the AND gate design it tests on the right, and the console below listing the testbench's reports as a table - time, file and line, simulation time and text - from the truth table to All tests passed

Nothing to set up. Click the TB or RTL badge to show the test, the design or both side by side.

See every signal. Hand it in as a figure.

Open a testbench and click Waveform. That’s it.

The waveform viewer in HDLBoard after a testbench run of an AND gate: the TB group with y, a, b, expected, i and j and the RTL group with a, b and y, drawn over 0 to 40 ns with the cursor at 3.0 ns. Expected is still undefined until 10 ns and is drawn as a red hatched band
Lab reportPB1180
The exported report figure: black traces of a, b and y on white, labelled on the left, with a time axis from 0 to 40 ns. y goes high at 30 ns, when both a and b are high
Fig. 1. Simulated AND gate: y is 1 only when a and b are both 1.

Paste it into your report

Figure for a report redraws the traces in view as a clean figure, sized for print the way IEEE asks. Copy it, or save it as PNG or SVG.

Point at a name. See where it lives.

Rest your mouse on a signal or port in HDLBoard's editor, or click it, and it lights up everywhere it appears in your code: where it's declared and every place it's used. No more scrolling up and down hunting for where sum was declared.

HDLBoard in split view with the testbench adder4_tb.vhdl on the left and the design adder4.vhd on the right. The signal sum is highlighted in blue: its declaration and its use in the port map sum => sum in the testbench, and the port sum and its assignment in the design

Side by side, it follows the wires: click sum in the testbench and the port it is connected to lights up in your design.

Your board. On screen.

Pick your board.
See familiar controls.

From the DE1-SoC’s switches to the Basys 3’s directional buttons, the simulation layout follows your board. Choose a built-in profile and work with its own port names, controls and displays.

Terasic

DE1-SoC

50 MHz

10 switches · 10 LEDs · 4 pushbuttons
6 independent 7-segment displays

DE1-SoC preview in HDLBoard: ten LEDs and switches, six HEX displays and four KEY buttons.
Digilent

Basys 3

100 MHz

16 switches · 16 LEDs · 5 directional buttons
4-digit multiplexed display

Basys 3 preview in HDLBoard: sixteen switches and LEDs, four display digits and five buttons arranged in a cross.

Five profiles are built in: DE1-SoC, DE10-Lite, Basys 3, Nexys A7 and Default.
The board-specific profiles use the manufacturers’ names for switches, LEDs and other controls.

Your workspace, your layout

Arrange the Board I/O controls in one or two columns.
Choose a layout in Settings, then resize the panel beside your code.

Settings layout selector with single column and two columns; two columns is selected.

Make room for your board

Start with a board.
Make it your own.

Different port names? A different number of switches? Open the board manager and make an editable copy of a built-in profile. Configure it with form fields and see the board preview update as you edit.

Read the board guide
Board settings editing a Basys 3 Custom profile. The component list is on the left; the right shows the five-button cross layout and editable btnU, btnL, btnC, btnR and btnD port names. Save changes is below.
Editing a copy of Basys 3. Select the screenshot to enlarge.

  1. Copy a starting point

    Go to Settings → Manage board, choose a profile and select Create editable copy.

  2. Set up your controls

    Edit port names, counts, button layouts and display settings. Valid changes appear in Board I/O.

  3. Keep it with your project

    Apply with Save changes, then save the project to keep its custom board configuration.

The My Projects dialog in HDLBoard, signed in as rlangoy: projects on this computer and on GitHub in one list, with the Full Adder Truth Table project expanded showing its description, owner, update date and GitHub and VHDL tags

All your projects. One list.

Projects on your computer and on GitHub show up side by side, so you never have to remember where you saved something.

  • Search across project names and files
  • Filter by type, sort by newest, switch between list and grid
  • Pick which folder on your computer holds your local projects

Store in the cloud. Share with others.

Save your projects to GitHub Gists, open them from anywhere, and share your work with teammates or your teacher.

  • One-click save to the cloud
  • Open the same project from any browser or the Windows app
  • Share a link so others can open and run your design

Get started

Made at USN for students new to FPGA design. Pick what suits you.

  • Try it now

    Runs in your browser. Nothing to install.

    Try online

  • Windows PC

    Install the app on your own PC.

    Download

  • Linux PC

    Run the AppImage on your own PC.

    Download

  • VirtualBox

    Run a ready-made virtual machine.

    Download

  • Classroom

    Host one copy for the whole class.

    Hosting guide

How it works

  1. 1

    Write

    Edit VHDL or Verilog source files in the browser.

  2. 2

    Simulate

    GHDL (VHDL) or Icarus (Verilog) compiles and runs your design.

  3. 3

    Watch it respond

    Results are drawn live onto the virtual board.

  4. 4

    Interact

    Flip switches and press buttons, and see the design react.

  5. 5

    Take it to the board

    Same pin names as the DE1-SoC: add a pin assignment in Quartus and program it.

Also in the box

  • Real-time pacing: a 1 Hz blink blinks once a second, as on the board
  • Testbenches without ports, with report and assert output live in the console
  • Hints for common mistakes, like did you mean range? for a misspelled keyword
  • Download one file or the whole project as a .zip
  • Save projects to your GitHub account and pick them up on any computer

What it is not

  • No synthesis, timing analysis or bitstream: use Quartus for the real board
  • Board profiles simulate their configured switches, buttons, LEDs and displays, not every peripheral on the physical board
  • In the browser, your work starts fresh every time you reload. Save to GitHub or download your files to keep them. (The Windows app preserves them automatically.)

Open source on GitHub

Read the code, report an issue or help make HDLBoard better. Guides and documentation live in the repository.

View on GitHub